Senior Silicon Diagnostics Engineer

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 8 years of experience in DFT, DFD, or DFM flows, methodologies, and silicon diagnostics.
• Experience in DFT-related verification, Gate-Level Simulations (GLS) and ATPG.

Preferred qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• Experience with CAD layout tools for physical fault isolation and cross-probing.
• In-depth understanding of scan-chain based logical tests and Scan Compression. Knowledge of Tessent based tools.
• High proficiency in scripting languages like Python, Perl, Tcl, or SKILL to automate complex volume diagnostic flows.
• Ability to work independently, lead projects, and collaborate effectively across global, multidisciplinary teams.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Silicon Diagnosis and Defect Isolation: Perform post-silicon electrical and physical fault isolation using production test results (e.g., error logs, flop mapping, and software-based diagnosis) to narrow down the cone of logic.
• Methodology Development: Develop, deploy, and automate volume diagnosis and data analysis flows. Generate and apply specialized diagnosis patterns for Soft-Defect-Location (SDL) or Laser-Voltage-Imaging (LVI).
• Cross-Functional Collaboration: Partner with Design, DFX, Verification, and Test teams to define requirements for highly diagnosable designs and to build layout databases for diagnosis and cross-probing.
• EFA and Root Cause Analysis: Define and execute Electrical Failure Analysis (EFA) workflows to root-cause yield issues, qualification failures, and customer returns.
• ATE and Pattern Debug: Lead silicon bring-up, debug, and validation of DFT features on Automated Test Equipment (ATE), debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG related issues.