Senior Principal Design Verification Engineer

Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field
7–10 years of hands-on DV experience in semiconductor/ASIC/SoC companies
Deep expertise in SystemVerilog and UVM (Universal Verification Methodology)
Strong understanding of digital design fundamentals — RTL, timing, clocking, resets
Experience with industry-standard simulators: Xcelium, VCS, Questa
Proficiency in coverage-driven verification — functional, code, and toggle coverage
Hands-on experience with formal verification tools and flows
Experience with bus protocols such as AXI, AHB, APB, PCIe, DDR, or similar
Strong debug skills — waveform analysis (Verisium, SimVision)
Familiarity with low-power verification (UPF/CPF) and gls/power-aware gls simulation

Core Responsibilities

Strategy and Architecture
Verification Planning: Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure.

Testbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.

Feature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.

Execution and Technical Leadership
Customer Interaction: Technically lead DV execution of small to mid-sized customer ASIC projects. Handle customer interactions. Convert high level customer requirements into DV execution plan.   

Development: Write complex test cases and sequences to achieve high functional coverage.

Debug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.

Constraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.

Formal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.

Metric Management
Coverage Analysis: Monitor and analyze functional and code coverage metrics.

Gate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior.

Sign-off: Define the "definition of done" and provide final technical approval for the verification phase.

Soft Skills and Leadership
Mentorship: Guiding junior engineers on coding standards and debugging techniques.

Cross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams.

Project Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.

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Experience Level

Senior Level